Since the early days of the semiconductor industry, the observation known as “Moore's Law” has been followed by the industry. This “law” states that the number of transistors that can economically be integrated into a semiconductor device increases by a factor of 1.5 to 2.0 times every two years. The increase has generally been achieved by miniaturization of the components of the electronic device, achieved through planer scaling of the transistor and interconnect wiring, and has provided the additional benefits of continuous improvements in processing power, data storage density and functional integration of semiconductor devices and the end products of which they are critical components. The current state-of-the-art semiconductor devices are built using a minimum critical dimension of about 28 nanometers, and smaller devices are in development.
In order to reduce the size of transistors and continue to improve semiconductor performance, it is necessary to create patterns on the silicon substrate in ever decreasing dimensions. Photolithography is the most common process used to create these patterns. The minimum feature size that can be lithographically patterned is generally limited to a factor of the wavelength of the illumination source. The state of the art illumination source used in lithographic manufacturing today uses illumination at a wavelength of 193 nanometers. In order to produce 28 nanometer features, a number of improvements have been employed, including the use of immersion optics to increase the numerical aperture (NA) of the lithographic system, the use of design modifications for the photomask, sometimes called optical proximity correction (OPC), to improve final image fidelity, and the use of multiple photo-exposures for patterning a single layer. These techniques, while making sub-wavelength patterning possible, add significant cost to the process.
Although single functional transistors with gate dimensions as small as 5 nm in size have been demonstrated, and manufacturing techniques have been proposed to enable large-scale patterning for devices with dimensions smaller than 10 nm, the cost effectiveness and commercial feasibility of these solutions have yet to be demonstrated.
An alternative to device shrinking that can enable the functional integration of ever greater numbers of semiconductor devices in a cost effective manner is the utilization of techniques that connect integrated devices vertically. New methods of attaching integrated circuits (ICs) to each other and to printed circuit boards (PCBs) are now being introduced. These new methods include silicon interposers and through-silicon vias (TSVs), so-called “3D IC” and “2.5D IC” technologies. The interconnections used for 3D and 2.5D packaging between stacked IC or semiconductor devices are much smaller than for PCBs. While PCBs rarely use interconnections smaller than a 50 micron minimum pitch dimension, commercial TSV packages can have diameters as small as 2 microns, and silicon interposers can have features with dimensions below 100 nanometers. Interposers can also be manufactured from glass, or a composite of organic material with fiberglass or a particle filler such as silica.
Integrated circuits are often manufactured using custom processes, depending on the device being manufactured. For example, dynamic random-access memory (DRAM) chips may require a different process recipe than complementary metal-oxide-semiconductor (CMOS) logic chips if each is to be manufactured for optimum performance. In the past, if a device that needed both memory and logic was desired, a chip design using both in the same IC could be manufactured, but with a compromise that optimized the performance of neither logic nor memory. Alternatively, a printed circuit board (PCB) could be manufactured, containing both a memory and a logic chip, each manufactured for optimum performance. However, the long distances that the signals would have to travel on the PCB from chip-to-chip will slow the performance considerably. As the clock speed of logic chips has increased and multiple operating cores have been introduced, memory-access latency resulting from traditional surface mount, through-hole interconnect, ball grid arrays (BGAs), or dual in-line memory module (DIMMs) on printed circuit boards has begun to limit the performance of more and more electronic systems.
Recently, it is becoming popular to stack ICs and connect them within the same package. One example of this new packaging technology is the silicon interposer that provides interconnection between two or more semiconductor devices, a semiconductor device and a printed circuit board, or a semiconductor device and some other package component. An active silicon device may also function as an interposer in which case the structure is typically referred to as “3D IC”. The interposer is typically a layer of silicon, manufactured from the same kind of silicon wafer used for the ICs themselves, in which vias that pass through the silicon have been manufactured. The vias, placed at predetermined locations, are holes filled with an electrically conducting material (such as copper (Cu)) that pass completely through the silicon. When chips are bonded to both sides of the interposer, the through-silicon vias (TSVs) allow signals from one IC to travel a relatively short distance vertically from one chip to another. When chips are bonded to a PCB using an interposer, they allow signals from the chips on one side of the interposer to connect the PCB.
Similar interposers with vias passing through the materials may also be fabricated using glass or a reinforced organic material.
These vias are typically made of copper (Cu), but processes using vias made of tungsten (W) have also been developed, and vias with a variety of metal layers are anticipated. Interposers with thickness of less than 50 microns with via diameters of about 5 microns have been demonstrated. Somewhat thicker interposers may be desirable for some manufacturing processes, but the thickness is typically limited by the practical of height to via diameter aspect ratio that can be reliably manufactured. Aspect ratio of 10:1 has been widely demonstrated and prototypes indicate aspect ratios of 20:1 are possible. A single interposer, serving as the interconnection between memory chips that can contain billions of memory cells and a logic chip for a microprocessor, can have thousands or even tens of thousands of TSVs. For thinner interposers, smaller TSV diameters (as small as 1 micron) have been proposed, allowing an even greater number of connections. Since each TSV is a vital communication link between a portion of the logic and memory chip, each TSV must function perfectly. No breakdown in communication can be allowed.
It is therefore imperative that, before the active chips are bonded together to the interposer, the interposer is known to be 100% functional. The economic need for this is clear—bonding good chips to a bad interposer ruins all the economic value invested in making the chips.
There is therefore a need to properly test and/or inspect these interposers before final bonding takes place.
Aside from interposers with TSVs, other packaging technologies are also being explored as a way to increase the number of transistors in a single package, and continue the benefits of Moore's Law.
Flip chip interconnect (FCI), sometimes called controlled collapse chip connection (or “C4”), is one such technology that is currently being used. In this process, a pad ring is connected to rows, columns or an array of solder bumps on the surface of a chip while it is still in the form of a wafer. The bumps may form an array on the surface of the chip, a partial array, or may exist in a single perimeter row around the chip or a column in the center or side. The bumps are may be aligned to either the package substrate or to another die.
In traditional processes, the individual chips are then “diced” or singulated from the wafer and placed onto a substrate which is typically composed of glass fiber reinforced epoxy (such as FR4), bismaleimide triazine (BT) or similar, but may also be ceramic or Teflon or other stable material, or even a flexible substrate such as tape. Solder flux may be first applied to the bump and or substrate contact surface or it may be a component of the solder paste applied during the process.
The bumped chip and substrate are passed through a mass reflow furnace. During this process the solder melts and re-solidifies. This melting and re-solidifying should produce the desired outcome of a reliable connection at each joint between every micro-bump and every land, pad or terminal on the associated substrate or die. Chips with about 2,000 bumps using this process have been demonstrated. The pitch of such bump arrays is typically larger than 100 microns.
After mass reflow, the solder joints created in this process may be inspected using acoustic microscopy. A sound wave is passed through the joint and either detected on the other side of the structure or reflected back to the sending side. Changes in the properties of the acoustic signal can be utilized to determine if the solder joint is normal or not.
This kind of immediate feedback provided by acoustic microscopy allows for rapid identification of problems and their correction by modification of the process, materials, and equipment used in the manufacture of such products.
Newer products are currently entering the market that require interconnect pitches of less than 100 microns. Single perimeter rows of bumps made from copper and attached to organic substrates have been demonstrated at a pitch of 50 microns, and dual rows of copper bumps attached to organic substrates have been demonstrated at a pitch of 80 microns. These chips are typically mounted to the substrate using a process known as thermo-compression bonding. As opposed to mass reflow, in thermo compression bonding, the bumped chip is aligned to the substrate, placed onto the substrate and then exposed to pressure and heat all using a single tool. Typically one chip is processed at a time, and processing times can exceed tens of seconds for each individual chip.
Newer products such as those applying silicon or other fine pitch interposers or 3D stacking of die onto active devices require a full array of contacts at pitches of 50 microns or smaller. The demands for even smaller and smaller pitch is expected to continue as chip to chip data rates expand.
For current parts being developed at this smaller bump pitch, there is no reliable non-destructive test methodology to inspect the quality of bonds formed during the bonding process. Acoustic microscopy has not demonstrated the ability to detect flaws in solder bumps at bump pitches of 50 microns and below. And, in many cases, the electrical contact points on the parts are too small even for electrical testing at this stage in the manufacturing process. So additional manufacturing steps must be performed at additional cost. In most cases, several days or weeks may be required until an electrical test is performed on an assembled package.
In many cases, due to the lack of feedback data during package assembly or bonding process, some or all of the units tested will be found to be non-functional. Current failure analysis techniques examine these failed parts mechanically, typically by using focused ion beam milling to locate the specific failed connection. The connection thus exposed can be imaged used existing scanning electron microscope techniques. The time required to create an image of a defected bond has been reported to be in the range of 1-2 weeks after electrical test due to the difficulty and time required to mill to the specific spot in question without going through or past it. This is unacceptable for high-speed production lines or package assembly.
There is therefore a need for a failure analysis technique that can non-destructively examine failed parts for process improvement, preferably in a matter of seconds, and then be used in a manufacturing line for statistical process control (SPC).
For the prior art testing of interposers, electrical probes can be used to make continuity tests of the TSVs. However, given that there may be tens of thousands of TSVs, a probe using tens of thousands of electrodes may be required. It is unclear if such a probe is even possible using standard testing techniques. Furthermore, such probes physically touch the ends of the TSVs, and must be jammed against the surface to insure good electrical continuity. This protocol may in fact leave what was a perfectly good interposer scratched and marred by the time the test is finished, while not revealing this in the data gathered by the probe while it was in contact.
The pitch of connections on an interposer or die is also smaller than conventional devices being either probed or contacted. Even at the current level of technology, mechanical contact by probes or contacts small enough for the next generation of TSVs, flip chip bumpers, or interposers is not readily available to accomplish such an electrical test.
In addition, many interposers have electrical connection between the top side and the bottom side of the interposer. Contact with probes would have to be to both sides of the interposer. This further increases the difficulty of manufacturing an electrical test mechanism for silicon interposers.
In IC manufacturing, inspection to confirm correct, defect-free manufacturing is routinely used to examine wafers and PCBs before proceeding to the next manufacturing step. Integrated circuits (ICs) are inspected at many steps in the process, from bare wafer inspection to inspecting printed circuit boards (PCBs) before and after attaching ICs. Different types of microscopes are used at different inspection points: electron and optical microscopes are often used for inspecting the ICs during the manufacturing process, and x-ray microscopes can be used for inspecting PCBs.
The inspection techniques using optical photons or electrons to inspect silicon wafers cannot be used to inspect 3D and 2.5D IC packages because they do not penetrate through the ICs or interposers sufficiently to provide an internal view of the packaged ICs. They are also not capable of performing inspection or metrology for partially packaged components, a critical requirement for process control. X-rays, however, can penetrate through many layers of packaging to provide an internal view of the assembled device.
The initial discovery of x-rays by Röntgen in 1895 [W. C. Röntgen, “Eine Neue Art von Strahlen (Würzburg Verlag, 1895); “On a New Kind of Rays,” Nature, Vol. 53, pp. 274-276 (Jan. 23 1896)] was in the form of shadowgraphs, in which the contrast of x-ray transmission for biological samples (e.g. bones vs. tissue) allowed internal structures to be revealed without damaging the samples themselves. However, because of their short wavelength (10 to 0.01 nm, corresponding to energies in the range of 100-100,000 eV), and the absence of materials for which the refractive index for x-rays differs significantly from 1, there are no easy equivalents to refractive or reflective optical elements so commonly used in optical system design. So, even now, the most common use of x-rays is still as a simple shadowgraph, observing the structure of bones and teeth in the offices of doctors and dentists.
Early x-ray “microscopy,” developed more than 50 years after the initial discovery of x-rays, simply consisted of elaborate shadowgraph apparatus, in which the diverging x-rays cast a shadow larger than the object [S. P. Newberry and S. E. Summers, U.S. Pat. No. 2,814,729]. With the advent of computer data collection, it became possible to gather more information from the specimen, changing the relative positions and illumination angles of the x-ray source and specimen in a systematic way. Using multiple transmission measurements taken at multiple angles around the specimen, images can be synthesized by computer that represent a 2-dimensional or 3-dimensional model of the specimen [G. N. Hounsfield, U.S. Pat. No. 3,778,614]. The “slices” of interior bodies so revealed are amazing to look at, revealing a great deal about the internal structures without invasive surgery. However, as far as the physics of the x-ray interaction with the specimen, these tomographic reconstructions represent nothing more than an elaborate map of x-ray absorption—a sophisticated shadowgraph.
Over time, other imaging tools for x-ray optical systems were invented. An apparatus using grazing incidence reflection from surfaces provided cone reflectors [C. G. Wang, U.S. Pat. No. 4,317,036] and capillary collimators [F. Kumasaka et al., U.S. Pat. No. 5,276,724] to allow a diverging x-ray beam to be manipulated into a collimated beam or to concentrate x-rays onto a specimen.
Systems using an x-ray microscope for the inspection of integrated circuits have been disclosed by the Xradia Corporation [W. Yun and Y. Wang, U.S. Pat. No. 7,119,953; Y. Wang et al., U.S. Pat. No. 7,394,890; M. Bajura et al., U.S. Pat. No. 8,139,846; <http://www.xradia.com/>]. FIG. 1 illustrates a prior art x-ray microscope system as disclosed on Drawing Sheet 2 of U.S. Pat. No. 7,119,953. In such a system, x-rays from a source 010 are collected by a condenser 012, which relays x-rays from the source 010 to a test object 020 to be examined. This condenser 012 is described in some embodiments as a capillary condenser with a suitably configured reflecting surface, while in others as a zone plate. The converging beam from the condenser 012 irradiates the test object 020 to be examined, and the radiation emerging from the test object 020 to be examined is scattered and diffracted out of the path of the direct radiation beam. An x-ray objective 041 is therefore used to form an image of the object, collecting the scattered x-rays. This objective 041 is described as being possibly a zone plate lens, a Wolter optic, or a Fresnel optic. In some embodiments, an additional phase plate 045, often in the form of a ring around the center axis of the system, is included to enhance contrast. Both the phase plate 045 and the objective 041 are described as being attached to a “high-transmissive substrate” 048 to form a composite optic 040. The focused radiation 051 forms an image of the test object 020 on a detector 050, which is described as possibly comprising in some embodiments a charge-coupled device (CCD), and in some embodiments comprising a scintillator, and in others being a film-based detector.
X-ray systems with Fresnel zone plate (FZP) optics such as this prior art Xradia system can be effective for the non-destructive examination of integrated circuits, but the limitations of the zone plate optics [J. Kirz and D. Attwood, “Zone Plates”, Sec. 4.4 of the “X-ray Data Booklet”<http://xdb.lbl.gov/Section4/Sec_4-4.html>] reduce the wavelength range over which x-rays can be effectively collected, thereby decreasing the collection efficiency and increasing the time to collect data for a complete IC. The system is therefore very slow and inefficient for collecting large volumes of data on multiple layers of an IC.
X-ray systems using point projection microscopy (PPM) provide another way to form images of ICs, PCBs, or other packaging structures such as interposers. These systems form direct shadows of objects using x-rays emitted from a small point source. Such a prior art x-ray inspection system is the XD7600NT manufactured by Nordson DAGE of Aylesbury, Buckinghamshire UK.
A schematic of a PPM system is illustrated in FIG. 2. In a PPM system, a “point” source 10 emits x-rays 11 at a wide range of angles. The object 20 to be examined comprising detailed structures 21 is placed some distance away, so that it casts an enlarged shadow 30 comprising features 31 corresponding to the structures 21 on a detection screen 50 some distance behind the object.
The advantage to such a system is its simplicity—it is a simple shadow projection, and the magnification can be increased by simply placing the detector farther away. By not using inefficient zone plates, higher intensity and therefore faster image collection times are achieved.
For an object of infinite thinness and with no internal structure, this may be adequate. Unfortunately, ICs and packaging materials are not infinitely thin; they have complex 3D structures, and the wide angular range of the shadow projection system means that identical features illuminated at an angle cast very different shadows from those same features illuminated head on. This parallax error, illustrated in FIG. 2, must be taken into account in the image analysis of any shadow projection system, and prevents its easy use in an inspection system, since pixel-by-pixel comparison is impossible for images taken with different illumination angles.
Resolution is also an issue with PPM systems. Although x-ray wavelengths can be chosen to be short enough that significant diffraction does not occur, blurring is still a significant problem. The “point” source is actually the spot where an electron beam collides with an anode, and a typical x-ray source spot is at least 1 micron in diameter. The resolution of the shadow is therefore limited by the size of the original source spot, and at some distance, the shadows from an extended source will blur.
This blurring is illustrated in FIG. 3. For an object 20 with an opaque feature 21 of width A, a “point” source 10 of size S a distance L1 away from the object 20 casts a shadow 31 of width A1 corresponding to the opaque feature 21. At the edge of the shadow 31, the extended source 10 also casts an extended penumbra 32 of width A2. The larger the extended source 10, the larger the penumbra 32, and the poorer the image contrast and resolution. [Note: a penumbra will appear on all sides of the shadow; only one is shown for illustrative purposes. It should also be noted that the penumbra for a PPM system will not be symmetric for off-axis features due to the parallax effects illustrated in FIG. 2.]
Throughput is therefore also an issue with PPM systems. To achieve the necessary resolution, all the x-rays must be emitted from as small a point as possible. Because x-rays are usually generated by colliding a beam of electrons into the surface of a metal, and there are therefore limits on the brightness that can be achieved from a single spot. Attempts to increase the current too high will not increase the brightness from the point source, but instead may simply melt the a hole in the anode. Attempts to increase the x-ray flux by extending the area of the source spot reduce the system resolution further. The x-ray target must generally be a thin foil, to limit the size of the x-ray spot due to electron scattering in the target. As a rule of thumb, approximately 1 watt of electron-beam energy can be deposited into a 1 micron spot on this type of x-ray target. Better resolution can only be obtained by reducing the size of the electron beam generating the x-rays, which in turn requires the beam current to be reduced to avoid thermal damage to the thin target. No existing x-ray source with spot size of 1 micron has been able to reliably operate at over 10 watts of power.
Therefore, existing x-ray systems lack sufficient resolution and imaging speed to meet the needs for high-resolution, high-throughput IC and electronic packaging inspection. Therefore, a new approach is needed to combine the penetrating power of x-rays with high-power, high-resolution, telecentric imaging techniques to provide measurement and inspection capabilities for the next generation of 3D and 2.5D integrated circuit packages, such as silicon interposers with TSVs.